NAND flash memories are widely used as memory devices for large-volume data. Currently, the reduction in cost per bit and the increase in capacity are being promoted by miniaturizing memory elements, and further progress in miniaturization in future is required. However, to further miniaturize the flash memories, there are many problems to be solved, such as the development of a lithographic technique, a short channel effect, interelement interference, and the control of variations in elements. Thus, it is highly likely that memory density cannot be continuously improved in future by merely developing a technique of miniaturization in a plane.
Therefore, in recent years, to improve the degree of integration of memory cells, developments for switching its structure from a conventional two-dimensional (planar) structure to a three-dimensional (solid) structure have been made, and various three-dimensional nonvolatile semiconductor memory devices have been proposed. A vertical-gate (VG) semiconductor memory structure, which is one of these, comprises semiconductor layers (channels) on a semiconductor substrate, and memory cells (for example, NAND cells) are provided in each semiconductor.
However, the semiconductor layers as channels become thinner and longer as the degree of integration of the memory cells is improved, and there has been a problem that the on-state current of the memory cells decreases because of an increase in channel resistance. This problem comes to the fore when polycrystalline materials (for example, polycrystalline silicon) are used as the semiconductor layers.